{"id":10021316,"date":"2026-03-18T19:23:21","date_gmt":"2026-03-18T11:23:21","guid":{"rendered":"https:\/\/itmax.cn\/?p=10021316"},"modified":"2026-03-18T19:23:21","modified_gmt":"2026-03-18T11:23:21","slug":"fpga%e7%9a%84%e9%80%89%e5%9e%8b%e5%92%8c%e5%ba%94%e7%94%a8","status":"publish","type":"post","link":"https:\/\/itmax.cn\/?p=10021316","title":{"rendered":"FPGA\u7684\u9009\u578b\u548c\u5e94\u7528"},"content":{"rendered":"<p>\u5927\u5bb6\u597d\uff0c\u6211\u662f\u826f\u8bb8\u3002<\/p>\n<p>\u6700\u8fd1\u6709\u4e0d\u5c11\u670b\u53cb\u95ee\u6211\u5173\u4e8e FPGA \u7684\u95ee\u9898\uff0c\u867d\u7136\u6211\u4e3b\u8981\u505a\u5d4c\u5165\u5f0f\u8f6f\u4ef6\u5f00\u53d1\uff0c\u4f46\u5728\u5b9e\u9645\u9879\u76ee\u4e2d\u4e5f\u7ecf\u5e38\u9700\u8981\u548c FPGA \u5de5\u7a0b\u5e08\u914d\u5408\u3002<\/p>\n<p>\u4eca\u5929\u5c31\u6765\u804a\u804a FPGA \u7684\u9009\u578b\u548c\u5e94\u7528\uff0c\u5e0c\u671b\u80fd\u7ed9\u51c6\u5907\u5165\u5751\u6216\u8005\u6b63\u5728\u9009\u578b\u7684\u670b\u53cb\u4e00\u4e9b\u53c2\u8003\u3002<\/p>\n<h2>1. FPGA \u57fa\u7840\u8ba4\u77e5<\/h2>\n<h3>1.1 \u4ec0\u4e48\u662f FPGA<\/h3>\n<p>FPGA\uff08Field Programmable Gate Array\uff0c\u73b0\u573a\u53ef\u7f16\u7a0b\u95e8\u9635\u5217\uff09\u662f\u4e00\u79cd\u53ef\u4ee5\u901a\u8fc7\u7f16\u7a0b\u6765\u914d\u7f6e\u5185\u90e8\u903b\u8f91\u7684\u96c6\u6210\u7535\u8def\u3002<\/p>\n<p>\u548c\u6211\u4eec\u5e38\u7528\u7684 MCU\u3001MPU \u4e0d\u540c\uff0cFPGA \u7684\u6838\u5fc3\u4f18\u52bf\u5728\u4e8e\u5e76\u884c\u5904\u7406\u80fd\u529b\u548c\u53ef\u91cd\u6784\u6027\u3002<\/p>\n<p>\u7b80\u5355\u6765\u8bf4\uff0cMCU \u662f\u987a\u5e8f\u6267\u884c\u6307\u4ee4\u7684\uff0c\u5c31\u50cf\u4e00\u4e2a\u4eba\u6309\u7167\u6e05\u5355\u9010\u9879\u5b8c\u6210\u4efb\u52a1\u3002<\/p>\n<p>\u800c FPGA \u53ef\u4ee5\u540c\u65f6\u5904\u7406\u591a\u4e2a\u4efb\u52a1\uff0c\u5c31\u50cf\u591a\u4e2a\u4eba\u540c\u65f6\u5de5\u4f5c\uff0c\u6548\u7387\u81ea\u7136\u9ad8\u5f97\u591a\u3002<\/p>\n<p>\u8fd9\u4e5f\u662f\u4e3a\u4ec0\u4e48\u5728\u9ad8\u901f\u4fe1\u53f7\u5904\u7406\u3001\u56fe\u50cf\u5904\u7406\u3001\u901a\u4fe1\u534f\u8bae\u8f6c\u6362\u7b49\u573a\u666f\u4e0b\uff0cFPGA \u6709\u7740\u4e0d\u53ef\u66ff\u4ee3\u7684\u5730\u4f4d\u3002<\/p>\n<h3>1.2 FPGA \u7684\u6838\u5fc3\u8d44\u6e90<\/h3>\n<p>\u5728\u9009\u578b\u4e4b\u524d\uff0c\u6211\u4eec\u9700\u8981\u4e86\u89e3 FPGA \u7684\u51e0\u4e2a\u6838\u5fc3\u8d44\u6e90\u6307\u6807\uff1a<\/p>\n<p><strong>\u903b\u8f91\u5355\u5143\uff08LE\/LUT\uff09<\/strong>\uff1a\u8fd9\u662f FPGA \u6700\u57fa\u672c\u7684\u903b\u8f91\u8d44\u6e90\uff0c\u7528\u6765\u5b9e\u73b0\u7ec4\u5408\u903b\u8f91\u548c\u65f6\u5e8f\u903b\u8f91\u3002<\/p>\n<p>\u903b\u8f91\u5355\u5143\u7684\u6570\u91cf\u76f4\u63a5\u51b3\u5b9a\u4e86\u4f60\u80fd\u5b9e\u73b0\u591a\u590d\u6742\u7684\u903b\u8f91\u529f\u80fd\u3002<\/p>\n<p>\u6bd4\u5982 Xilinx \u7684 Artix-7 \u7cfb\u5217\uff0c\u4ece\u51e0\u4e07\u5230\u51e0\u5341\u4e07\u903b\u8f91\u5355\u5143\u4e0d\u7b49\u3002<\/p>\n<p><strong>\u5757 RAM\uff08BRAM\uff09<\/strong>\uff1a\u7247\u4e0a\u5b58\u50a8\u8d44\u6e90\uff0c\u901f\u5ea6\u5feb\u4f46\u5bb9\u91cf\u6709\u9650\u3002<\/p>\n<p>\u5728\u505a\u6570\u636e\u7f13\u5b58\u3001FIFO\u3001\u67e5\u627e\u8868\u7b49\u5e94\u7528\u65f6\u975e\u5e38\u91cd\u8981\u3002<\/p>\n<p>\u6211\u4e4b\u524d\u505a\u8fc7\u4e00\u4e2a\u56fe\u50cf\u5904\u7406\u9879\u76ee\uff0c\u9700\u8981\u7f13\u5b58\u591a\u5e27\u56fe\u50cf\u6570\u636e\uff0cBRAM \u8d44\u6e90\u5c31\u6210\u4e86\u74f6\u9888\u3002<\/p>\n<p><strong>DSP \u5355\u5143<\/strong>\uff1a\u4e13\u95e8\u7528\u4e8e\u4e58\u6cd5\u3001\u52a0\u6cd5\u7b49\u6570\u5b66\u8fd0\u7b97\u7684\u786c\u6838\uff0c\u5728\u6570\u5b57\u4fe1\u53f7\u5904\u7406\u4e2d\u975e\u5e38\u5173\u952e\u3002<\/p>\n<p>\u5982\u679c\u4f60\u7684\u5e94\u7528\u6d89\u53ca\u5927\u91cf\u6570\u5b66\u8fd0\u7b97\uff0cDSP \u8d44\u6e90\u4e00\u5b9a\u8981\u591f\u7528\u3002<\/p>\n<p><strong>IO \u5f15\u811a<\/strong>\uff1a\u8fd9\u4e2a\u5f88\u597d\u7406\u89e3\uff0c\u5c31\u662f\u5bf9\u5916\u901a\u4fe1\u7684\u63a5\u53e3\u3002<\/p>\n<p>\u4e0d\u540c\u5c01\u88c5\u7684 FPGA\uff0cIO \u6570\u91cf\u5dee\u5f02\u5f88\u5927\uff0c\u4ece\u51e0\u5341\u5230\u4e0a\u5343\u4e0d\u7b49\u3002<\/p>\n<p><strong>\u65f6\u949f\u8d44\u6e90<\/strong>\uff1a\u5305\u62ec PLL\u3001DLL \u7b49\uff0c\u7528\u4e8e\u65f6\u949f\u7ba1\u7406\u548c\u9891\u7387\u7efc\u5408\u3002<\/p>\n<p>\u9ad8\u901f\u5e94\u7528\u5bf9\u65f6\u949f\u8d28\u91cf\u8981\u6c42\u5f88\u9ad8\uff0c\u8fd9\u5757\u8d44\u6e90\u4e5f\u4e0d\u80fd\u5ffd\u89c6\u3002<\/p>\n<h2>2. FPGA \u9009\u578b\u8981\u70b9<\/h2>\n<h3>2.1 \u660e\u786e\u5e94\u7528\u9700\u6c42<\/h3>\n<p>\u9009\u578b\u7684\u7b2c\u4e00\u6b65\u662f\u660e\u786e\u4f60\u7684\u5e94\u7528\u573a\u666f\u3002<\/p>\n<p>\u6211\u89c1\u8fc7\u4e0d\u5c11\u65b0\u624b\u4e0a\u6765\u5c31\u9009\u6700\u8d35\u6700\u9ad8\u7aef\u7684\u578b\u53f7\uff0c\u7ed3\u679c\u53d1\u73b0\u8d44\u6e90\u6d6a\u8d39\u4e25\u91cd\uff0c\u6210\u672c\u4e5f\u63a7\u5236\u4e0d\u4f4f\u3002<\/p>\n<p><strong>\u9ad8\u901f\u6570\u636e\u91c7\u96c6<\/strong>\uff1a\u6bd4\u5982\u793a\u6ce2\u5668\u3001\u9ad8\u901f ADC \u63a5\u53e3\uff0c\u9700\u8981\u5173\u6ce8 IO \u901f\u7387\u3001SERDES \u8d44\u6e90\u3002<\/p>\n<p>\u6211\u4e4b\u524d\u53c2\u4e0e\u7684\u4e00\u4e2a\u9879\u76ee\uff0c\u9700\u8981\u63a5\u5165 4 \u8def 1Gsps \u7684 ADC\uff0c\u6700\u540e\u9009\u62e9\u4e86\u5e26\u6709\u9ad8\u901f SERDES \u7684 Kintex-7 \u7cfb\u5217\u3002<\/p>\n<p><strong>\u56fe\u50cf\u5904\u7406<\/strong>\uff1a\u9700\u8981\u5927\u91cf\u7684 DSP \u8d44\u6e90\u548c BRAM\u3002<\/p>\n<p>\u6bd4\u5982\u505a\u5b9e\u65f6\u56fe\u50cf\u6ee4\u6ce2\u3001\u8fb9\u7f18\u68c0\u6d4b\uff0cDSP \u5355\u5143\u7684\u6570\u91cf\u76f4\u63a5\u5f71\u54cd\u80fd\u5904\u7406\u7684\u56fe\u50cf\u5206\u8fa8\u7387\u548c\u5e27\u7387\u3002<\/p>\n<p><strong>\u901a\u4fe1\u534f\u8bae\u8f6c\u6362<\/strong>\uff1a\u6bd4\u5982 PCIe\u3001\u4ee5\u592a\u7f51\u3001CAN\u3001\u4e32\u53e3\u7b49\u534f\u8bae\u4e4b\u95f4\u7684\u8f6c\u6362\uff0c\u9700\u8981\u5173\u6ce8\u786c\u6838 IP \u7684\u652f\u6301\u60c5\u51b5\u3002<\/p>\n<p>\u6709\u4e9b\u9ad8\u7aef FPGA \u96c6\u6210\u4e86 PCIe \u786c\u6838\uff0c\u53ef\u4ee5\u5927\u5927\u7b80\u5316\u8bbe\u8ba1\u3002<\/p>\n<p><strong>\u5de5\u63a7\u5e94\u7528<\/strong>\uff1a\u5bf9\u53ef\u9760\u6027\u8981\u6c42\u9ad8\uff0c\u9700\u8981\u8003\u8651\u5de5\u4e1a\u7ea7\u6e29\u5ea6\u8303\u56f4\uff08-40\u2103 \u5230 85\u2103 \u6216\u66f4\u9ad8\uff09\u3001\u6297\u5e72\u6270\u80fd\u529b\u7b49\u3002<\/p>\n<h3>2.2 \u8d44\u6e90\u8bc4\u4f30\u65b9\u6cd5<\/h3>\n<p>\u5982\u4f55\u8bc4\u4f30\u9700\u8981\u591a\u5c11\u8d44\u6e90\u5462\uff1f<\/p>\n<p>\u8fd9\u91cc\u6709\u4e2a\u7ecf\u9a8c\u516c\u5f0f\uff0c\u4f46\u5b9e\u9645\u9879\u76ee\u4e2d\u8fd8\u9700\u8981\u9884\u7559 30% \u5230 50% \u7684\u4f59\u91cf\uff1a<\/p>\n<p><strong>\u903b\u8f91\u8d44\u6e90<\/strong>\uff1a\u5148\u7528 HDL\uff08Verilog \u6216 VHDL\uff09\u5199\u51fa\u6838\u5fc3\u6a21\u5757\uff0c\u7528\u7efc\u5408\u5de5\u5177\u8bc4\u4f30\u8d44\u6e90\u5360\u7528\u3002<\/p>\n<p>\u6bd4\u5982\u4e00\u4e2a\u7b80\u5355\u7684 UART \u6a21\u5757\u53ef\u80fd\u53ea\u9700\u8981\u51e0\u767e\u4e2a\u903b\u8f91\u5355\u5143\uff0c\u4f46\u4e00\u4e2a\u590d\u6742\u7684\u56fe\u50cf\u5904\u7406\u6d41\u6c34\u7ebf\u53ef\u80fd\u9700\u8981\u51e0\u4e07\u751a\u81f3\u5341\u51e0\u4e07\u3002<\/p>\n<p><strong>\u5b58\u50a8\u8d44\u6e90<\/strong>\uff1a\u8ba1\u7b97\u6570\u636e\u7f13\u5b58\u9700\u6c42\u3002\u6bd4\u5982\u7f13\u5b58\u4e00\u5e27 1920&#215;1080 \u7684 RGB \u56fe\u50cf\uff0c\u9700\u8981 1920 <em>1080<\/em>3 = 6220800 \u5b57\u8282\uff0c\u7ea6 6MB\u3002<\/p>\n<p>\u5982\u679c BRAM \u4e0d\u591f\uff0c\u5c31\u9700\u8981\u5916\u6302 DDR\u3002<\/p>\n<p><strong>DSP \u8d44\u6e90<\/strong>\uff1a\u7edf\u8ba1\u4e58\u6cd5\u5668\u548c\u52a0\u6cd5\u5668\u7684\u6570\u91cf\u3002<\/p>\n<p>\u6bd4\u5982\u4e00\u4e2a FIR \u6ee4\u6ce2\u5668\uff0c\u5982\u679c\u6709 N \u4e2a\u62bd\u5934\uff0c\u5c31\u9700\u8981 N \u4e2a\u4e58\u6cd5\u5668\u548c N-1 \u4e2a\u52a0\u6cd5\u5668\u3002<\/p>\n<h3>2.3 \u5382\u5546\u548c\u7cfb\u5217\u9009\u62e9<\/h3>\n<p>\u76ee\u524d\u5e02\u573a\u4e0a\u4e3b\u8981\u6709\u4e09\u5927 FPGA \u5382\u5546\uff1a<\/p>\n<p><strong>Xilinx\uff08\u73b0\u5728\u662f AMD \u7684\u4e00\u90e8\u5206\uff09<\/strong>\uff1a\u5e02\u573a\u5360\u6709\u7387\u6700\u9ad8\uff0c\u4ea7\u54c1\u7ebf\u6700\u5168\u3002<\/p>\n<p>\u4ece\u4f4e\u7aef\u7684 Spartan \u7cfb\u5217\u5230\u9ad8\u7aef\u7684 Virtex \u7cfb\u5217\uff0c\u5e94\u6709\u5c3d\u6709\u3002<\/p>\n<p>\u5f00\u53d1\u5de5\u5177 Vivado \u529f\u80fd\u5f3a\u5927\uff0c\u4f46\u5b66\u4e60\u66f2\u7ebf\u7a0d\u9661\u3002<\/p>\n<p>\u6211\u4e2a\u4eba\u7528\u5f97\u6700\u591a\u7684\u662f Artix-7 \u548c Zynq \u7cfb\u5217\u3002<\/p>\n<p><strong>Intel\uff08Altera\uff09<\/strong>\uff1a\u539f\u6765\u7684 Altera \u88ab Intel \u6536\u8d2d\u540e\uff0c\u4ea7\u54c1\u7ebf\u4e5f\u5f88\u4e30\u5bcc\u3002<\/p>\n<p>Cyclone \u7cfb\u5217\u6027\u4ef7\u6bd4\u9ad8\uff0cStratix \u7cfb\u5217\u6027\u80fd\u5f3a\u608d\u3002\u5f00\u53d1\u5de5\u5177 Quartus \u4e5f\u5f88\u6210\u719f\u3002<\/p>\n<p><strong>Lattice<\/strong>\uff1a\u4e3b\u6253\u4f4e\u529f\u8017\u548c\u5c0f\u5c01\u88c5\uff0c\u5728\u4fbf\u643a\u8bbe\u5907\u548c IoT \u9886\u57df\u6709\u4f18\u52bf\u3002<\/p>\n<p>\u4ef7\u683c\u76f8\u5bf9\u4fbf\u5b9c\uff0c\u4f46\u751f\u6001\u4e0d\u5982\u524d\u4e24\u5bb6\u3002<\/p>\n<p>\u5bf9\u4e8e\u521d\u5b66\u8005\u6216\u8005\u4e2d\u5c0f\u578b\u9879\u76ee\uff0c\u6211\u63a8\u8350\u4ece Xilinx \u7684 Artix-7 \u6216 Intel \u7684 Cyclone V \u5f00\u59cb\u3002<\/p>\n<p>\u8fd9\u4e24\u4e2a\u7cfb\u5217\u6027\u4ef7\u6bd4\u9ad8\uff0c\u8d44\u6599\u4e30\u5bcc\uff0c\u793e\u533a\u6d3b\u8dc3\u3002<\/p>\n<h3>2.4 \u6210\u672c\u8003\u91cf<\/h3>\n<p>FPGA \u7684\u6210\u672c\u4e0d\u4ec5\u4ec5\u662f\u82af\u7247\u672c\u8eab\u7684\u4ef7\u683c\uff0c\u8fd8\u5305\u62ec\uff1a<\/p>\n<p><strong>\u5f00\u53d1\u677f\u6210\u672c<\/strong>\uff1a\u5982\u679c\u662f\u539f\u578b\u9a8c\u8bc1\uff0c\u53ef\u4ee5\u4e70\u73b0\u6210\u7684\u5f00\u53d1\u677f\uff0c\u4ef7\u683c\u4ece\u51e0\u767e\u5230\u51e0\u5343\u4e0d\u7b49\u3002<\/p>\n<p>\u6bd4\u5982 Digilent \u7684 Arty A7 \u5f00\u53d1\u677f\uff0c\u642d\u8f7d Artix-7\uff0c\u4ef7\u683c\u5728 1000 \u5143\u5de6\u53f3\uff0c\u975e\u5e38\u9002\u5408\u5b66\u4e60\u548c\u5c0f\u578b\u9879\u76ee\u3002<\/p>\n<p><strong>\u5f00\u53d1\u5de5\u5177<\/strong>\uff1aXilinx \u548c Intel \u7684\u5f00\u53d1\u5de5\u5177\u90fd\u6709\u514d\u8d39\u7248\u672c\uff0c\u4f46\u9ad8\u7ea7\u529f\u80fd\u9700\u8981\u4ed8\u8d39 License\u3002<\/p>\n<p>\u5bf9\u4e8e\u5546\u4e1a\u9879\u76ee\uff0c\u8fd9\u5757\u6210\u672c\u4e0d\u80fd\u5ffd\u89c6\u3002<\/p>\n<p><strong>PCB \u6210\u672c<\/strong>\uff1aFPGA \u7684\u5c01\u88c5\u901a\u5e38\u662f BGA\uff0c\u5bf9 PCB \u8bbe\u8ba1\u548c\u5236\u9020\u8981\u6c42\u8f83\u9ad8\u3002<\/p>\n<p>\u5982\u679c\u662f\u591a\u5c42\u677f\uff0c\u6210\u672c\u4f1a\u663e\u8457\u589e\u52a0\u3002<\/p>\n<p><strong>\u91cf\u4ea7\u6210\u672c<\/strong>\uff1a\u6279\u91cf\u91c7\u8d2d\u65f6\uff0c\u82af\u7247\u4ef7\u683c\u4f1a\u6709\u6298\u6263\uff0c\u4f46\u9700\u8981\u8003\u8651\u4f9b\u8d27\u5468\u671f\u548c\u6700\u5c0f\u8d77\u8ba2\u91cf\u3002<\/p>\n<h2>3. FPGA \u5178\u578b\u5e94\u7528\u6848\u4f8b<\/h2>\n<h3>3.1 \u9ad8\u901f\u6570\u636e\u91c7\u96c6\u7cfb\u7edf<\/h3>\n<p>\u6211\u4e4b\u524d\u53c2\u4e0e\u8fc7\u4e00\u4e2a\u96f7\u8fbe\u4fe1\u53f7\u5904\u7406\u9879\u76ee\uff0c\u9700\u8981\u91c7\u96c6 8 \u8def 100MHz \u7684 ADC \u6570\u636e\uff0c\u5e76\u8fdb\u884c\u5b9e\u65f6 FFT \u8fd0\u7b97\u3002<\/p>\n<p>\u8fd9\u79cd\u5e94\u7528 MCU \u5b8c\u5168\u65e0\u6cd5\u80dc\u4efb\uff0c\u5fc5\u987b\u7528 FPGA\u3002<\/p>\n<p>\u8bbe\u8ba1\u601d\u8def\u662f\u8fd9\u6837\u7684\uff1aFPGA \u901a\u8fc7 LVDS \u63a5\u53e3\u63a5\u6536 ADC \u6570\u636e\uff0c\u5148\u505a\u6570\u636e\u5bf9\u9f50\u548c\u65f6\u949f\u57df\u8f6c\u6362\uff0c\u7136\u540e\u9001\u5165 FFT IP \u6838\u8fdb\u884c\u9891\u57df\u5206\u6790\uff0c\u6700\u540e\u901a\u8fc7 PCIe \u63a5\u53e3\u5c06\u7ed3\u679c\u4f20\u7ed9\u4e3b\u673a\u3002<\/p>\n<p>\u6574\u4e2a\u6570\u636e\u6d41\u6c34\u7ebf\u5728 FPGA \u5185\u90e8\u5e76\u884c\u5904\u7406\uff0c\u5ef6\u8fdf\u53ea\u6709\u51e0\u5fae\u79d2\u3002<\/p>\n<p>\u5173\u952e\u4ee3\u7801\u7247\u6bb5\uff08Verilog\uff09\uff1a<\/p>\n<pre><code>\/\/ ADC\u6570\u636e\u63a5\u6536\u6a21\u5757\nmodule adc_receiver (\n    input wire clk,\n    input wire rst_n,\n    input wire [7:0] adc_data_p,\n    input wire [7:0] adc_data_n,\n    output reg [15:0] data_out,\n    output reg data_valid\n);\n\u200b\n\/\/ LVDS\u5dee\u5206\u8f93\u5165\u7f13\u51b2\nwire [7:0] adc_data;\ngenvar i;\ngenerate\n    for (i = 0; i &lt; 8; i = i + 1) begin : lvds_buf\n        IBUFDS #(\n            .DIFF_TERM(&quot;TRUE&quot;)\n        ) ibufds_inst (\n            .I(adc_data_p[i]),\n            .IB(adc_data_n[i]),\n            .O(adc_data[i])\n        );\n    end\nendgenerate\n\u200b\n\/\/ \u6570\u636e\u62fc\u63a5\u548c\u5bf9\u9f50\nreg [7:0] data_buf;\nreg phase;\n\u200b\nalways @(posedge clk or negedge rst_n) begin\n    if (!rst_n) begin\n        data_buf &lt;= 8'b0;\n        data_out &lt;= 16'b0;\n        data_valid &lt;= 1'b0;\n        phase &lt;= 1'b0;\n    end else begin\n        if (phase == 1'b0) begin\n            data_buf &lt;= adc_data;\n            data_valid &lt;= 1'b0;\n            phase &lt;= 1'b1;\n        end else begin\n            data_out &lt;= {data_buf, adc_data};\n            data_valid &lt;= 1'b1;\n            phase &lt;= 1'b0;\n        end\n    end\nend\n\u200b\nendmodule<\/code><\/pre>\n<p>\u8fd9\u4e2a\u6a21\u5757\u5b9e\u73b0\u4e86 LVDS \u5dee\u5206\u4fe1\u53f7\u63a5\u6536\u548c\u6570\u636e\u62fc\u63a5\u3002<\/p>\n<p>\u5b9e\u9645\u9879\u76ee\u4e2d\u8fd8\u9700\u8981\u52a0\u5165 FIFO \u7f13\u51b2\u3001\u65f6\u949f\u57df\u8f6c\u6362\u7b49\u6a21\u5757\u3002<\/p>\n<h3>3.2 \u89c6\u9891\u56fe\u50cf\u5904\u7406<\/h3>\n<p>\u53e6\u4e00\u4e2a\u5e38\u89c1\u5e94\u7528\u662f\u5b9e\u65f6\u89c6\u9891\u5904\u7406\u3002<\/p>\n<p>\u6bd4\u5982\u5728\u5b89\u9632\u76d1\u63a7\u4e2d\uff0c\u9700\u8981\u5bf9\u6444\u50cf\u5934\u91c7\u96c6\u7684\u89c6\u9891\u8fdb\u884c\u964d\u566a\u3001\u589e\u5f3a\u3001\u76ee\u6807\u68c0\u6d4b\u7b49\u5904\u7406\u3002<\/p>\n<p>FPGA \u5728\u8fd9\u7c7b\u5e94\u7528\u4e2d\u7684\u4f18\u52bf\u975e\u5e38\u660e\u663e\uff1a\u53ef\u4ee5\u5b9e\u73b0\u50cf\u7d20\u7ea7\u5e76\u884c\u5904\u7406\uff0c\u5ef6\u8fdf\u4f4e\uff0c\u529f\u8017\u76f8\u5bf9 GPU \u4e5f\u66f4\u4f4e\u3002<\/p>\n<p>\u6211\u89c1\u8fc7\u4e00\u4e2a\u9879\u76ee\uff0c\u7528 FPGA \u5b9e\u73b0\u4e86 4K@60fps \u7684\u5b9e\u65f6\u89c6\u9891\u5904\u7406\uff0c\u5982\u679c\u7528 ARM \u5904\u7406\u5668\uff0c\u6839\u672c\u4e0d\u53ef\u80fd\u8fbe\u5230\u8fd9\u4e2a\u6027\u80fd\u3002<\/p>\n<p>\u5178\u578b\u7684\u89c6\u9891\u5904\u7406\u6d41\u6c34\u7ebf\u5305\u62ec\uff1a<\/p>\n<p>1.1 \u89c6\u9891\u8f93\u5165\u63a5\u53e3\uff08MIPI\u3001HDMI \u7b49\uff091.2 \u56fe\u50cf\u9884\u5904\u7406\uff08\u53bb\u566a\u3001\u8272\u5f69\u7a7a\u95f4\u8f6c\u6362\uff091.3 \u6838\u5fc3\u7b97\u6cd5\uff08\u6ee4\u6ce2\u3001\u8fb9\u7f18\u68c0\u6d4b\u3001\u7279\u5f81\u63d0\u53d6\uff091.4 \u540e\u5904\u7406\uff08\u53e0\u52a0 OSD\u3001\u7f29\u653e\uff091.5 \u89c6\u9891\u8f93\u51fa\u63a5\u53e3<\/p>\n<p>\u6bcf\u4e2a\u6a21\u5757\u90fd\u53ef\u4ee5\u7528\u72ec\u7acb\u7684\u786c\u4ef6\u903b\u8f91\u5b9e\u73b0\uff0c\u6570\u636e\u5728\u6d41\u6c34\u7ebf\u4e2d\u6d41\u52a8\uff0c\u5b9e\u73b0\u771f\u6b63\u7684\u5b9e\u65f6\u5904\u7406\u3002<\/p>\n<h3>3.3 \u901a\u4fe1\u534f\u8bae\u6865\u63a5<\/h3>\n<p>\u5728\u5d4c\u5165\u5f0f\u7cfb\u7edf\u4e2d\uff0c\u7ecf\u5e38\u9700\u8981\u5728\u4e0d\u540c\u901a\u4fe1\u534f\u8bae\u4e4b\u95f4\u8f6c\u6362\u3002<\/p>\n<p>\u6bd4\u5982\u5c06\u4ee5\u592a\u7f51\u6570\u636e\u8f6c\u6362\u4e3a CAN \u603b\u7ebf\u6570\u636e\uff0c\u6216\u8005\u5c06\u591a\u8def\u4e32\u53e3\u6570\u636e\u6c47\u805a\u5230\u4e00\u4e2a\u9ad8\u901f\u63a5\u53e3\u3002<\/p>\n<p>\u6211\u4e4b\u524d\u505a\u8fc7\u4e00\u4e2a\u9879\u76ee\uff0c\u9700\u8981\u5c06 16 \u8def RS485 \u4e32\u53e3\u6570\u636e\u901a\u8fc7\u5343\u5146\u4ee5\u592a\u7f51\u4e0a\u4f20\u5230\u670d\u52a1\u5668\u3002<\/p>\n<p>\u5982\u679c\u7528 MCU \u5b9e\u73b0\uff0c16 \u8def\u4e32\u53e3\u7684\u4e2d\u65ad\u5904\u7406\u5c31\u4f1a\u975e\u5e38\u590d\u6742\uff0c\u800c\u4e14\u5bb9\u6613\u4e22\u6570\u636e\u3002<\/p>\n<p>\u7528 FPGA \u5c31\u7b80\u5355\u591a\u4e86\uff0c\u6bcf\u8def\u4e32\u53e3\u7528\u4e00\u4e2a\u72ec\u7acb\u7684 UART \u6a21\u5757\uff0c\u6570\u636e\u5148\u7f13\u5b58\u5230 FIFO\uff0c\u7136\u540e\u7531\u4ef2\u88c1\u6a21\u5757\u7edf\u4e00\u6253\u5305\u6210\u4ee5\u592a\u7f51\u5e27\u53d1\u9001\u3002<\/p>\n<p>\u5173\u952e\u662f FPGA \u7684\u5e76\u884c\u5904\u7406\u80fd\u529b\uff0c16 \u4e2a UART \u6a21\u5757\u540c\u65f6\u5de5\u4f5c\uff0c\u4e92\u4e0d\u5e72\u6270\uff0c\u7cfb\u7edf\u7684\u5b9e\u65f6\u6027\u548c\u53ef\u9760\u6027\u90fd\u5f97\u5230\u4e86\u4fdd\u8bc1\u3002<\/p>\n<h3>3.4 SoC \u7cfb\u7edf\u8bbe\u8ba1<\/h3>\n<p>\u73b0\u5728\u5f88\u591a FPGA \u96c6\u6210\u4e86 ARM \u5904\u7406\u5668\uff0c\u6bd4\u5982 Xilinx \u7684 Zynq \u7cfb\u5217\u548c Intel \u7684 SoC FPGA \u7cfb\u5217\u3002<\/p>\n<p>\u8fd9\u79cd\u67b6\u6784\u7ed3\u5408\u4e86\u5904\u7406\u5668\u7684\u7075\u6d3b\u6027\u548c FPGA \u7684\u5e76\u884c\u5904\u7406\u80fd\u529b\uff0c\u975e\u5e38\u9002\u5408\u590d\u6742\u7684\u5d4c\u5165\u5f0f\u7cfb\u7edf\u3002<\/p>\n<p>\u4ee5 Zynq-7000 \u4e3a\u4f8b\uff0c\u5b83\u5305\u542b\u53cc\u6838 ARM Cortex-A9 \u5904\u7406\u5668\u548c FPGA \u903b\u8f91\u3002<\/p>\n<p>ARM \u7aef\u8fd0\u884c Linux \u7cfb\u7edf\uff0c\u8d1f\u8d23\u7cfb\u7edf\u7ba1\u7406\u3001\u7f51\u7edc\u901a\u4fe1\u3001\u7528\u6237\u754c\u9762\u7b49\uff1bFPGA \u7aef\u8d1f\u8d23\u9ad8\u901f\u6570\u636e\u5904\u7406\u3001\u5916\u8bbe\u63a5\u53e3\u7b49\u3002<\/p>\n<p>\u4e24\u8005\u901a\u8fc7 AXI \u603b\u7ebf\u9ad8\u901f\u4e92\u8054\uff0c\u53ef\u4ee5\u5b9e\u73b0\u975e\u5e38\u590d\u6742\u7684\u529f\u80fd\u3002<\/p>\n<p>\u6211\u7528 Zynq \u505a\u8fc7\u4e00\u4e2a\u5de5\u4e1a\u76f8\u673a\u9879\u76ee\uff0cARM \u7aef\u8fd0\u884c Linux\uff0c\u8d1f\u8d23\u7f51\u7edc\u901a\u4fe1\u548c\u53c2\u6570\u914d\u7f6e\uff1bFPGA \u7aef\u5b9e\u73b0\u56fe\u50cf\u4f20\u611f\u5668\u63a5\u53e3\u3001ISP \u5904\u7406\u3001\u56fe\u50cf\u538b\u7f29\u7b49\u3002<\/p>\n<p>\u6574\u4e2a\u7cfb\u7edf\u6027\u80fd\u5f3a\u5927\uff0c\u5f00\u53d1\u6548\u7387\u4e5f\u5f88\u9ad8\u3002<\/p>\n<h2>4. FPGA \u5f00\u53d1\u6ce8\u610f\u4e8b\u9879<\/h2>\n<h3>4.1 \u65f6\u5e8f\u7ea6\u675f<\/h3>\n<p>FPGA \u8bbe\u8ba1\u4e2d\u6700\u5bb9\u6613\u51fa\u95ee\u9898\u7684\u5c31\u662f\u65f6\u5e8f\u3002<\/p>\n<p>\u4e0d\u50cf MCU \u7f16\u7a0b\uff0cFPGA \u7684\u65f6\u5e8f\u662f\u786c\u4ef6\u7ea7\u522b\u7684\uff0c\u5fc5\u987b\u6ee1\u8db3\u5efa\u7acb\u65f6\u95f4\u548c\u4fdd\u6301\u65f6\u95f4\u7684\u8981\u6c42\u3002<\/p>\n<p>\u5728 Vivado \u4e2d\uff0c\u9700\u8981\u7f16\u5199 XDC \u7ea6\u675f\u6587\u4ef6\uff0c\u5b9a\u4e49\u65f6\u949f\u9891\u7387\u3001IO \u5ef6\u8fdf\u7b49\u53c2\u6570\u3002\u6bd4\u5982\uff1a<\/p>\n<pre><code># \u521b\u5efa\u4e3b\u65f6\u949f\uff0c\u9891\u7387100MHz\ncreate_clock -period 10.000 -name sys_clk [get_ports clk_in]\n\u200b\n# \u8bbe\u7f6e\u8f93\u5165\u5ef6\u8fdf\nset_input_delay -clock sys_clk -max 2.000 [get_ports data_in]\nset_input_delay -clock sys_clk -min 0.500 [get_ports data_in]\n\u200b\n# \u8bbe\u7f6e\u8f93\u51fa\u5ef6\u8fdf\nset_output_delay -clock sys_clk -max 3.000 [get_ports data_out]\nset_output_delay -clock sys_clk -min 0.500 [get_ports data_out]<\/code><\/pre>\n<p>\u65f6\u5e8f\u7ea6\u675f\u4e0d\u5f53\u4f1a\u5bfc\u81f4\u7efc\u5408\u540e\u7684\u7535\u8def\u65e0\u6cd5\u7a33\u5b9a\u5de5\u4f5c\uff0c\u8fd9\u662f\u5f88\u591a\u521d\u5b66\u8005\u5bb9\u6613\u8e29\u7684\u5751\u3002<\/p>\n<h3>4.2 \u8de8\u65f6\u949f\u57df\u5904\u7406<\/h3>\n<p>\u5728 FPGA \u8bbe\u8ba1\u4e2d\uff0c\u7ecf\u5e38\u9700\u8981\u5728\u4e0d\u540c\u65f6\u949f\u57df\u4e4b\u95f4\u4f20\u9012\u6570\u636e\u3002<\/p>\n<p>\u5982\u679c\u5904\u7406\u4e0d\u5f53\uff0c\u4f1a\u51fa\u73b0\u4e9a\u7a33\u6001\uff0c\u5bfc\u81f4\u6570\u636e\u9519\u8bef\u3002<\/p>\n<p>\u5e38\u7528\u7684\u8de8\u65f6\u949f\u57df\u5904\u7406\u65b9\u6cd5\u5305\u62ec\uff1a<\/p>\n<p><strong>\u53cc\u89e6\u53d1\u5668\u540c\u6b65<\/strong>\uff1a\u9002\u7528\u4e8e\u5355\u6bd4\u7279\u4fe1\u53f7\uff0c\u7528\u4e24\u7ea7\u5bc4\u5b58\u5668\u540c\u6b65\uff0c\u964d\u4f4e\u4e9a\u7a33\u6001\u6982\u7387\u3002<\/p>\n<p><strong>\u5f02\u6b65 FIFO<\/strong>\uff1a\u9002\u7528\u4e8e\u591a\u6bd4\u7279\u6570\u636e\uff0cFIFO \u7684\u8bfb\u5199\u7aef\u5206\u522b\u5de5\u4f5c\u5728\u4e0d\u540c\u65f6\u949f\u57df\uff0c\u5185\u90e8\u7528\u683c\u96f7\u7801\u6307\u9488\u907f\u514d\u4e9a\u7a33\u6001\u3002<\/p>\n<p><strong>\u63e1\u624b\u534f\u8bae<\/strong>\uff1a\u7528\u8bf7\u6c42-\u5e94\u7b54\u673a\u5236\u786e\u4fdd\u6570\u636e\u4f20\u8f93\u7684\u53ef\u9760\u6027\u3002<\/p>\n<p>\u8fd9\u4e9b\u90fd\u662f FPGA \u8bbe\u8ba1\u7684\u57fa\u672c\u529f\uff0c\u5fc5\u987b\u638c\u63e1\u3002<\/p>\n<h3>4.3 \u8d44\u6e90\u4f18\u5316<\/h3>\n<p>FPGA \u8d44\u6e90\u6709\u9650\uff0c\u9700\u8981\u5408\u7406\u4f18\u5316\u3002\u5e38\u7528\u7684\u4f18\u5316\u65b9\u6cd5\u5305\u62ec\uff1a<\/p>\n<p><strong>\u6d41\u6c34\u7ebf\u8bbe\u8ba1<\/strong>\uff1a\u5c06\u590d\u6742\u7684\u7ec4\u5408\u903b\u8f91\u62c6\u5206\u6210\u591a\u7ea7\u6d41\u6c34\u7ebf\uff0c\u63d0\u9ad8\u5de5\u4f5c\u9891\u7387\u3002<\/p>\n<p>\u6bd4\u5982\u4e00\u4e2a\u590d\u6742\u7684\u4e58\u52a0\u8fd0\u7b97\uff0c\u53ef\u4ee5\u62c6\u5206\u6210\u4e58\u6cd5\u7ea7\u3001\u52a0\u6cd5\u7ea7\u3001\u8f93\u51fa\u7ea7\uff0c\u6bcf\u7ea7\u63d2\u5165\u5bc4\u5b58\u5668\u3002<\/p>\n<p><strong>\u8d44\u6e90\u590d\u7528<\/strong>\uff1a\u5bf9\u4e8e\u4e0d\u540c\u65f6\u5de5\u4f5c\u7684\u6a21\u5757\uff0c\u53ef\u4ee5\u590d\u7528\u76f8\u540c\u7684\u786c\u4ef6\u8d44\u6e90\u3002<\/p>\n<p>\u6bd4\u5982\u591a\u4e2a\u6ee4\u6ce2\u5668\u53ef\u4ee5\u5206\u65f6\u590d\u7528\u540c\u4e00\u7ec4\u4e58\u6cd5\u5668\u3002<\/p>\n<p><strong>IP \u6838\u4f7f\u7528<\/strong>\uff1aXilinx \u548c Intel \u90fd\u63d0\u4f9b\u4e86\u4e30\u5bcc\u7684 IP \u6838\uff0c\u6bd4\u5982 FFT\u3001FIR \u6ee4\u6ce2\u5668\u3001DDR \u63a7\u5236\u5668\u7b49\u3002<\/p>\n<p>\u4f7f\u7528 IP \u6838\u53ef\u4ee5\u8282\u7701\u5f00\u53d1\u65f6\u95f4\uff0c\u800c\u4e14\u7ecf\u8fc7\u4f18\u5316\uff0c\u6027\u80fd\u548c\u8d44\u6e90\u5360\u7528\u90fd\u6bd4\u8f83\u597d\u3002<\/p>\n<h3>4.4 \u4eff\u771f\u548c\u8c03\u8bd5<\/h3>\n<p>FPGA \u5f00\u53d1\u79bb\u4e0d\u5f00\u4eff\u771f\u548c\u8c03\u8bd5\u3002<\/p>\n<p>\u7efc\u5408\u524d\u7684\u529f\u80fd\u4eff\u771f\u53ef\u4ee5\u9a8c\u8bc1\u903b\u8f91\u6b63\u786e\u6027\uff0c\u7efc\u5408\u540e\u7684\u65f6\u5e8f\u4eff\u771f\u53ef\u4ee5\u53d1\u73b0\u65f6\u5e8f\u95ee\u9898\u3002<\/p>\n<p>\u5e38\u7528\u7684\u4eff\u771f\u5de5\u5177\u5305\u62ec ModelSim\u3001Vivado Simulator \u7b49\u3002<\/p>\n<p>\u7f16\u5199\u5b8c\u6574\u7684 testbench \u975e\u5e38\u91cd\u8981\uff0c\u53ef\u4ee5\u8986\u76d6\u5404\u79cd\u8fb9\u754c\u6761\u4ef6\u548c\u5f02\u5e38\u60c5\u51b5\u3002<\/p>\n<p>\u786c\u4ef6\u8c03\u8bd5\u65b9\u9762\uff0c\u53ef\u4ee5\u4f7f\u7528\u903b\u8f91\u5206\u6790\u4eea\uff08ILA\uff09\u6293\u53d6\u5185\u90e8\u4fe1\u53f7\uff0c\u6216\u8005\u901a\u8fc7 JTAG \u63a5\u53e3\u5728\u7ebf\u8c03\u8bd5\u3002<\/p>\n<p>Xilinx \u7684 ChipScope \u548c Intel \u7684 SignalTap \u90fd\u662f\u5f88\u597d\u7528\u7684\u5728\u7ebf\u8c03\u8bd5\u5de5\u5177\u3002<\/p>\n<h2>5. \u5b66\u4e60\u5efa\u8bae<\/h2>\n<p>\u5982\u679c\u4f60\u662f\u521a\u63a5\u89e6 FPGA \u7684\u65b0\u624b\uff0c\u6211\u7684\u5efa\u8bae\u662f\uff1a<\/p>\n<p><strong>\u4ece\u57fa\u7840\u5b66\u8d77<\/strong>\uff1a\u5148\u5b66\u4e60\u6570\u5b57\u7535\u8def\u57fa\u7840\uff0c\u7406\u89e3\u7ec4\u5408\u903b\u8f91\u3001\u65f6\u5e8f\u903b\u8f91\u3001\u72b6\u6001\u673a\u7b49\u6982\u5ff5\u3002<\/p>\n<p>\u7136\u540e\u5b66\u4e60 HDL \u8bed\u8a00\uff0cVerilog \u6216 VHDL \u90fd\u53ef\u4ee5\uff0c\u4e2a\u4eba\u63a8\u8350 Verilog\uff0c\u8bed\u6cd5\u66f4\u63a5\u8fd1 C \u8bed\u8a00\u3002<\/p>\n<p><strong>\u52a8\u624b\u5b9e\u8df5<\/strong>\uff1a\u4e70\u4e00\u5757\u5f00\u53d1\u677f\uff0c\u4ece LED \u6d41\u6c34\u706f\u3001\u6309\u952e\u6d88\u6296\u3001\u6570\u7801\u7ba1\u663e\u793a\u7b49\u7b80\u5355\u9879\u76ee\u5f00\u59cb\u3002<\/p>\n<p>\u7136\u540e\u9010\u6b65\u5c1d\u8bd5 UART \u901a\u4fe1\u3001VGA \u663e\u793a\u3001DDR \u8bfb\u5199\u7b49\u590d\u6742\u9879\u76ee\u3002<\/p>\n<p><strong>\u5b66\u4e60 IP \u6838\u4f7f\u7528<\/strong>\uff1a\u719f\u6089\u5382\u5546\u63d0\u4f9b\u7684 IP \u6838\uff0c\u6bd4\u5982\u65f6\u949f\u7ba1\u7406\u3001\u5b58\u50a8\u63a7\u5236\u5668\u3001\u901a\u4fe1\u63a5\u53e3\u7b49\u3002<\/p>\n<p>\u8fd9\u4e9b IP \u6838\u7ecf\u8fc7\u5145\u5206\u9a8c\u8bc1\uff0c\u53ef\u4ee5\u5927\u5927\u63d0\u9ad8\u5f00\u53d1\u6548\u7387\u3002<\/p>\n<p><strong>\u5173\u6ce8\u65f6\u5e8f<\/strong>\uff1a\u4ece\u4e00\u5f00\u59cb\u5c31\u517b\u6210\u826f\u597d\u7684\u65f6\u5e8f\u8bbe\u8ba1\u4e60\u60ef\uff0c\u5b66\u4f1a\u7f16\u5199\u7ea6\u675f\u6587\u4ef6\uff0c\u5206\u6790\u65f6\u5e8f\u62a5\u544a\u3002<\/p>\n<p>\u65f6\u5e8f\u95ee\u9898\u662f FPGA \u8bbe\u8ba1\u4e2d\u6700\u5e38\u89c1\u4e5f\u6700\u96be\u8c03\u8bd5\u7684\u95ee\u9898\u3002<\/p>\n<p><strong>\u591a\u770b\u9879\u76ee\u6848\u4f8b<\/strong>\uff1aGitHub \u4e0a\u6709\u5f88\u591a\u5f00\u6e90\u7684 FPGA \u9879\u76ee\uff0c\u53ef\u4ee5\u5b66\u4e60\u522b\u4eba\u7684\u8bbe\u8ba1\u601d\u8def\u548c\u4ee3\u7801\u98ce\u683c\u3002<\/p>\n<p>\u6bd4\u5982 PicoRV32\u3001VexRiscv \u7b49\u5f00\u6e90\u5904\u7406\u5668\u6838\uff0c\u90fd\u662f\u5f88\u597d\u7684\u5b66\u4e60\u8d44\u6599\u3002<\/p>\n<p>FPGA \u662f\u4e00\u4e2a\u95e8\u69db\u8f83\u9ad8\u4f46\u975e\u5e38\u6709\u4ef7\u503c\u7684\u6280\u672f\u65b9\u5411\u3002<\/p>\n<p>\u867d\u7136\u6211\u4e3b\u8981\u505a\u8f6f\u4ef6\u5f00\u53d1\uff0c\u4f46\u5728\u5b9e\u9645\u9879\u76ee\u4e2d\uff0c\u8f6f\u786c\u7ed3\u5408\u624d\u80fd\u53d1\u6325\u6700\u5927\u7684\u4ef7\u503c\u3002<\/p>\n<p>\u5e0c\u671b\u8fd9\u7bc7\u6587\u7ae0\u80fd\u5e2e\u52a9\u5927\u5bb6\u66f4\u597d\u5730\u7406\u89e3 FPGA \u7684\u9009\u578b\u548c\u5e94\u7528\uff0c\u5982\u679c\u6709\u95ee\u9898\u6b22\u8fce\u4ea4\u6d41\u8ba8\u8bba\u3002<\/p>\n<p><strong>\u66f4\u591a\u7f16\u7a0b\u5b66\u4e60\u8d44\u6e90<\/strong><\/p>\n<ul>\n<li><a href=\"https:\/\/link.segmentfault.com\/?enc=67Yc712mXSceWWl43qJugQ%3D%3D.PvB0MDuzu0f0Y3u40gGiReC%2FqsW3VLZ%2FAC%2F3olcM5XreH5ZNmO%2F1N0lIqEjE7wGLCDHrIWe1WdmqLLr0MXSUTA%3D%3D\" rel=\"nofollow noopener noreferrer\" target=\"_blank\">C \u8bed\u8a00\u96f6\u57fa\u7840\u5165\u95e8\u7535\u5b50\u4e66-2026 \u6700\u65b0\u7248<\/a><\/li>\n<li><a href=\"https:\/\/link.segmentfault.com\/?enc=3Xns%2B2cHHnLMe6EduL4Lvg%3D%3D.1w8D2Y6L4NilPkk%2FPgBikbdTBpkzau7ieGZNprE4V8mAdZ8To8qzGVutSzbfqmyFwronE11ElzmBlP9aAxg5TA%3D%3D\" rel=\"nofollow noopener noreferrer\" target=\"_blank\">STM32 \u96f6\u57fa\u7840\u5165\u95e8\u7535\u5b50\u4e66-2026 \u6700\u65b0\u7248<\/a><\/li>\n<li><a href=\"https:\/\/link.segmentfault.com\/?enc=hkE5F%2Fhmp5fWiXrcEa2B2w%3D%3D.ZslTEffmO6S4rznbeNi%2F%2BtwXafn8SI%2Fe3DnaQNK4SxmbFL8QhpW8ZFu7KYNJH2JqrU01yQDa0BAWKH2%2FQahI%2Be%2FaILqexOk2ZVXHBxLZ2lU%3D\" rel=\"nofollow noopener noreferrer\" target=\"_blank\">FreeRTOS \u96f6\u57fa\u7840\u5165\u95e8\u7535\u5b50\u4e66-2026 \u6700\u65b0\u7248<\/a><\/li>\n<li><a href=\"https:\/\/link.segmentfault.com\/?enc=xueMaLP4RLx%2B8cUtIxz%2FCw%3D%3D.IUhjhYNRKLCwjNdstFZiXUTrdNgYyW71gwUUnUdS8sJtBHULh%2FOlDv%2FWzG0ExfxhFGqdxMKhPVl5%2BW8oI0tJew%3D%3D\" rel=\"nofollow noopener noreferrer\" target=\"_blank\">C++ \u96f6\u57fa\u7840\u5165\u95e8\u7535\u5b50\u4e66-2026 \u6700\u65b0\u7248<\/a><\/li>\n<li><a href=\"https:\/\/link.segmentfault.com\/?enc=LgkvaQvGXKeeF32j8VsZCg%3D%3D.Z0EyxxlEU0ME5SSCDQzXgCRRXzMMaMm5Y3uh7GuD9l2UqqMFSFGfPFfoygLgmAVF6%2FBUbJVj9Miq9HsoZIj6aQ%3D%3D\" rel=\"nofollow noopener noreferrer\" target=\"_blank\">51 \u5355\u7247\u673a\u96f6\u57fa\u7840\u5165\u95e8\u5b66\u4e60\u8def\u7ebf<\/a><\/li>\n<li><a href=\"https:\/\/link.segmentfault.com\/?enc=IAWwI%2BOrWbpdO0iUv2WvBw%3D%3D.fqEC%2FLRhQ2%2FROhCtFCcQYRcXlrOrXltGatIMzlr3p3zRq5wOxoSFYDnXnslOAAjEPgKRl2%2F5Myis9JMPdrJz0w%3D%3D\" rel=\"nofollow noopener noreferrer\" target=\"_blank\">AD \u753b\u677f\u96f6\u57fa\u7840\u5165\u95e8\u5b66\u4e60\u8def\u7ebf<\/a><\/li>\n<li><a href=\"https:\/\/link.segmentfault.com\/?enc=vGlU6019oi3hDCZEy2CS2g%3D%3D.aroNMxOtjYui5P6O8FeuTWItbG2yYcJD7i7TSlvMrQUcrhMDniqRSAAziQvThtEu4J8e1h%2BY23CJwNtdlPKcaA%3D%3D\" rel=\"nofollow noopener noreferrer\" target=\"_blank\">C \u8bed\u8a00\u96f6\u57fa\u7840\u5165\u95e8\u5b66\u4e60\u8def\u7ebf<\/a><\/li>\n<li><a href=\"https:\/\/link.segmentfault.com\/?enc=bf3qx01ngz0%2FoCJv6vzhoA%3D%3D.hE5AoGRwVGWlKNjIoGb1MeNlmPZcUvslEwmlUlxlKbS%2FhzttF%2FnPQ%2FUTc0F5WTpEfDknxQPH4N0m9JhpdVTxmQ%3D%3D\" rel=\"nofollow noopener noreferrer\" target=\"_blank\">C++ \u8bed\u8a00\u96f6\u57fa\u7840\u5165\u95e8\u5b66\u4e60\u8def\u7ebf<\/a><\/li>\n<li><a href=\"https:\/\/link.segmentfault.com\/?enc=Dj2Ha1MMyjXoh%2Fv199kB%2BA%3D%3D.3NoAgS5NVG6TNPrFjswPR5Tg8dd2ChHB%2BOSIrh4yWOvT3wYdnSdgx15DC8XsDHm29mlULuGvrt380sVpyfR4LDXRSN22mw%2FmlHJuy%2FKTIrA%3D\" rel=\"nofollow noopener noreferrer\" target=\"_blank\">ESP32 \u96f6\u57fa\u7840\u5165\u95e8\u5b66\u4e60\u8def\u7ebf<\/a><\/li>\n<li><a href=\"https:\/\/link.segmentfault.com\/?enc=YwYEe%2BNP4K1Vz1gwBm5YSw%3D%3D.b41disJbwZ53Etc9E2%2BdvATJxpRa0FeuQRGlEIpfrMrQNeFHIRQybgNkGA%2BiRAC%2FszDlH2weIp2LLJ3gm0y032tAMA1WZq2CJVmbbqwunwE%3D\" rel=\"nofollow noopener noreferrer\" target=\"_blank\">FreeRTOS \u96f6\u57fa\u7840\u5165\u95e8\u5b66\u4e60\u8def\u7ebf<\/a><\/li>\n<li><a href=\"https:\/\/link.segmentfault.com\/?enc=fGzMc2DgvdztZMEavpStcA%3D%3D.o7jsWAQaojech7OZEeyItfxqD9YsFo59Z2UcK4z6%2Bcl4ajsKbmc%2BfB7NvCaDWJ5lGxfeJRVy0YWoWnOjr3a6jEmscuoQKYBNAAla7xEKYls%3D\" rel=\"nofollow noopener noreferrer\" target=\"_blank\">Linux \u5e94\u7528\u5f00\u53d1\u96f6\u57fa\u7840\u5165\u95e8\u5b66\u4e60\u8def\u7ebf<\/a><\/li>\n<li><a href=\"https:\/\/link.segmentfault.com\/?enc=vfLmwr1nQ2eX1w2kJCUTag%3D%3D.7VxOd2mJ%2FoMcIA%2FfL4D%2BGS153xo9vXuJRVzWWqzONKhmRjfXLeO5VlhwMsYQwcQNFf7UPapirIlM6%2FIvcLENzuC674P4yXcIbYOTjxTebBE%3D\" rel=\"nofollow noopener noreferrer\" target=\"_blank\">Linux \u5e95\u5c42\u5f00\u53d1\u96f6\u57fa\u7840\u5165\u95e8\u5b66\u4e60\u8def\u7ebf<\/a><\/li>\n<li><a href=\"https:\/\/link.segmentfault.com\/?enc=sinL52uwE75djG2LeQxy4g%3D%3D.D9ZsOFXkb5aERReOQEoaKoy1W8YGZ88CyI0aMgYz4xinS9JdBMNuIT%2BlaGdmVSmxK4mefDBI5CrfyeGH0aaSEw%3D%3D\" rel=\"nofollow noopener noreferrer\" target=\"_blank\">LVGL \u96f6\u57fa\u7840\u5165\u95e8\u5b66\u4e60\u8def\u7ebf<\/a><\/li>\n<li><a href=\"https:\/\/link.segmentfault.com\/?enc=RX31eXqXiPRMCmfwCBbJ2A%3D%3D.LkU1gR70fqicI0CRT%2Be4wOhIHPMpr8gzA3XQWyPf97hfP8IG9pFEp5tSreFISv6QVU3F1xoTp0DfV4UhkSotDw%3D%3D\" rel=\"nofollow noopener noreferrer\" target=\"_blank\">QT \u96f6\u57fa\u7840\u5165\u95e8\u5b66\u4e60\u8def\u7ebf<\/a><\/li>\n<li><a href=\"https:\/\/link.segmentfault.com\/?enc=8Ft8vxqRNlRjZgytQbsgWA%3D%3D.q0sUs7ywqwZsKIaTYSQA%2FOdVMtfgmB0H83CBFoETQlq6QH8cDnqd9Rro8QA31%2BkdzvZ786YoB20oamcvmcvtpEFsjh9OuzL2mhr%2FPgGBrog%3D\" rel=\"nofollow noopener noreferrer\" target=\"_blank\">STM32 \u96f6\u57fa\u7840\u5165\u95e8\u5b66\u4e60\u8def\u7ebf<\/a><\/li>\n<\/ul>\n<p><a href=\"https:\/\/segmentfault.com\/a\/1190000047659920\">https:\/\/segmentfault.com\/a\/1190000047659920<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>\u5927\u5bb6\u597d\uff0c\u6211\u662f\u826f\u8bb8\u3002 \u6700\u8fd1\u6709\u4e0d\u5c11\u670b\u53cb\u95ee\u6211\u5173\u4e8e FPGA \u7684\u95ee\u9898\uff0c\u867d\u7136\u6211\u4e3b\u8981\u505a\u5d4c\u5165\u5f0f\u8f6f\u4ef6\u5f00\u53d1\uff0c\u4f46\u5728\u5b9e\u9645\u9879\u76ee\u4e2d\u4e5f\u7ecf\u5e38 [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[4],"tags":[],"class_list":["post-10021316","post","type-post","status-publish","format-standard","hentry","category-share"],"jetpack_sharing_enabled":true,"jetpack_featured_media_url":"","_links":{"self":[{"href":"https:\/\/itmax.cn\/index.php?rest_route=\/wp\/v2\/posts\/10021316","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/itmax.cn\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/itmax.cn\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/itmax.cn\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/itmax.cn\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=10021316"}],"version-history":[{"count":0,"href":"https:\/\/itmax.cn\/index.php?rest_route=\/wp\/v2\/posts\/10021316\/revisions"}],"wp:attachment":[{"href":"https:\/\/itmax.cn\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=10021316"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/itmax.cn\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=10021316"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/itmax.cn\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=10021316"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}